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Low on-resistance and low trapping effects in 1200 V superlattice GaN-on-silicon heterostructures
Archive ouverte : Communication dans un congrès
Edité par HAL CCSD
International audience. Significant efforts are currently deployed in order to find optimum GaN-on-silicon epitaxial structuresenabling outstanding DC performances beyond 1 kV while delivering low trapping effects. We report on thedevelopment of GaN-on-silicon heterostructures, designed and manufactured by the company EpiGaNtargeting 1200 V power applications. In particular, it is shown that the insertion of superlattices (SL) into thebuffer layers allows pushing the vertical breakdown voltage above 1200 V without generating additionaltrapping effects as compared to a more standard step-graded AlGaN-based epi-structure using similar totalbuffer thickness. DC characterizations by means of back-gating measurements of fabricated transistorsreflect both the enhancement of the breakdown voltage and the low trapping effects up to 1200 V. Theseresults show that a proper buffer optimization along with the insertion of SL pave the way to GaN-on-siliconlateral power transistors operating at 1200 V with low on-resistance and low trapping effects.Two buffer layers have been compared: one reference buffer without SL with a total thickness of5.5µm and one SL-based buffer with a total thickness of 5µm. Vertical and lateral breakdown voltages havebeen measured at various temperatures. A vertical breakdown of 1300 V at 0.01 A/cm² is reached for thestructure with SL compared to 1000 V for the more standard structure, even though the latter is slightlythicker. Furthermore, it can be noticed that a low vertical leakage current is observed up to a temperatureof 150°C for the SL heterostructure. The leakage current increase up to 150°C is significantly lower than thereference buffer without SL. Also, the lateral breakdown voltage (floating substrate) is well-above 2000V forboth structures when using large contact distances.The effects of buffer traps have been studied through substrate bias ramp measurements usingvarious sweep rates. The reference heterostructure without SL shows low trapping effect up to 800V with astrong trapping activation starting from 900 V. However, the optimized SL buffer uniformly delivers state-ofthe-art low trapping effects all the way to 1300 V.Electrical characterizations have been realized on 2x50 µm transistors with a gate length of 2 µm forseveral gate-drain distances (GD) for both structures. DC characteristics ID-VD and ID-VG reveal a low leakagecurrent and an excellent pinch-off behavior reflecting the absence of parasitic punch-through effect or gateleakage current. It can be noticed that low static on-state resistance (RON_STATIC) of about 5 mΩ/cm² with agate-drain distance of 5 µm has been obtained. For larger GD, RON_STATIC increases as expected but remains stillbelow 15 mΩ/cm² for a GD = 40 µm for instance. Trapping in the buffer (between the 2DEG and the substrate)can be studied by back-gating operation with high vertical drain-to-substrate potential. In this case, tuningthe transistor / substrate bias conditions allows in turn to distinguish the surface and bulk traps. In the presentstudy, this technique has been applied and fully confirms the low buffer trapping up to 1200 V despite residualsurface traps due to the processing that still needs to be optimized.
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