Analog Duty Cycle Controller Using Backgate Body Biasing For 5G Millimeter Wave Applications

Archive ouverte : Communication dans un congrès

Beauquier, Clément | Duperray, David | Jabbour, Chadi | Desgreys, Patricia | Frappé, Antoine | Kaiser, Andreas

Edité par HAL CCSD

POSTER. International audience. This work presents the first 21-43 GHz CMOS analog Duty Cycle Controller (DCC) implemented in 28 nm FDSOI. The main application is millimeter wave mixers with CMOS digital signals. The proposed circuit corrects the input duty cycle with a negative feedback analog loop. Observability of the duty cycle is made through a passive low pass filter and the control is achieved by modifying the rise and fall time of the input clock signal, via backgate biasing of an inverter chain. The circuit has been validated by post layout, Monte-Carlo and corner simulations. At 28 GHz, the duty cycle correction range varies from 40 % to 55 %, and the additional power consumption introduced by the correction loop is frequency independent and is equal to 0.6 mW.

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